1. Field of the Invention
The present invention relates to field-effect transistors.
2. Description of the Related Art
Field-effect transistors are employed in many of today's circuits. Field-effect transistors are, for example, used as driver transistors for circuits or as bit line isolating transistors for isolating bit lines, etc. With ever increasing requirements to circuits in which field-effect transistors are used, high switching speeds on the one hand and a small area consumption on a chip or wafer on the other hand are required for field-effect transistors. At the same time, the field-effect transistor should have the largest possible current efficiency, i.e. the largest possible source-drain current per layout area with a predetermined gate voltage.
A transistor which is as wide as possible, the current efficiency of which determines the switching speed obtainable, has been used for this in the prior art. Put differently, a well-known transistor has a width of the channel region defined by the circuit layout for obtaining a current efficiency. According to the well-known formula R=ρ1/A, a low resistance and thus a high current efficiency are obtained by selecting a large width entering in the area A of the above formula. The width of a channel region can be thought of as a dimension formed in parallel to the substrate and perpendicular to a connection line between the source region and the drain region between edges or limits of the channel region. In general, the width of the channel region is thus perpendicular to the source-drain current direction.
FIG. 1 shows a well-known driver transistor in which a semiconductor substrate region 100 is formed over a large area in the form of a rectangle. A source terminal electrode 102, a drain terminal electrode 104 and a gate terminal electrode 106 are arranged on the semiconductor substrate region 100, wherein the gate terminal electrode 106 is generally separated from the semiconductor substrate region 100 by a gate oxide layer (not shown in FIG. 1). As is illustrated in FIG. 1, the source terminal electrode 102, the drain terminal electrode 104 and the gate terminal electrode 106 are formed in an elongate shape and arranged to one another in parallel. The gate terminal electrode 106 comprises a gate-contacting region 108 outside the semiconductor substrate region 100. The channel region of the driver transistor is formed in the semiconductor region 100 below the gate terminal electrode 106, wherein in the semiconductor substrate region 100 below the gate terminal electrode 106, the channel region is connected to a source region in the semiconductor substrate region 100 which is associated to the source terminal electrode 102 on one side and is connected to a drain region in the semiconductor substrate region 100 which is associated to the drain terminal electrode 104 on the other side. A field of application of field-effect transistors includes isolating bit lines. Thus, in the prior art a plurality of bit line isolating transistors are summarized to a bit line isolating assembly.
Referring to FIG. 2, an assembly of well-known bit line isolating transistors will be explained subsequently. The assembly includes three bit line isolating transistors 200a, 200b and 200c, each of which is arranged in a semiconductor substrate region 202a, 202b, 202c. Each bit line isolating transistor 200a, 200b, 200c comprises a source terminal electrode 204a, 204b, 204c and a drain terminal electrode 206a, 206b, 206c. A common gate terminal electrode 208 extends over all three bit line isolating transistors 200a, 200b, 200c between the source terminal electrodes 204a, 204b, 204c and the drain terminal electrodes 206a, 206b, 206c. Below the common gate terminal electrode 208, a channel region is formed in each semiconductor substrate region 202a, 202b, 202c of the bit line isolating transistors 200a, 200b, 200c, i.e. one channel region below the common gate terminal electrode 208 per semiconductor substrate region 202a, 202b, 202c. Each bit line isolating transistor 200a, 200b, 200c, in the semiconductor substrate region 202a, 202b, 202c, comprises a source region associated to the respective source terminal electrode 204a, 204b, 204c and a drain region associated to the respective drain terminal electrode 206a, 206b, 206c, wherein the channel region of each bit line isolating transistor 200a, 200b, 200c is formed between the source and drain regions of each bit line isolating transistor 200a, 200b, 200c and, in the semiconductor substrate region of the respective transistor, is connected to the source region of one side and connected to the drain region on the opposite side.
The assembly illustrated above forms a bit line isolator enabling each bit line connected to the source and drain terminal electrodes 204a, 204b, 204c and 206a, 206b and 206c to be isolated electrically by means of applying a suitable potential to the gate terminal electrode 208, so that an electric connection on the bit line is interrupted due to the pinch-off of the conductive channel caused by the potential.
The usage of the transistors described above, however, limits the overall capacity of the line driven by it with predetermined speed requirements. This means that the channel resistance R is set by selecting the width of the channel region such that an RC time constant τ=1/RC influencing the switching speed obtainable is obtained. Consequently, there is a conflict between obtaining the highest possible switching speed, wherein the largest possible channel widths are required for this, and obtaining a high component density per chip area unit. Put differently, the point is to obtain a higher current efficiency at the same time with a smaller area consumption compared to the prior art. Consequently, it has to be determined for each special circuit whether a limit of the area consumption or a high switching speed is desired, whereupon a circuit layout of the transistor is selected correspondingly. Thus, it would be desirable to improve the current efficiency of a transistor with a limited channel width, in particular in dynamic semiconductor circuits, such as, for example, in a bit line isolator.